Addition and subtraction of multi digit decimal operands are disclosed by the following publications: Hill and Patterson, "Digital Logic and Microprocessors" published by Wiley & Sons, New York 1984, pages 113-123; Omond, "Computer Arithmetic Systems, Algorithms, Architecture and Implementation", published by Prentice Hall, Englewood Cliffs, USA, 1994, pages 447-456; and Stein and Munro, "Introduction to Machine Arithmetic", Addison-Wesley Pulishing Company, Inc. New York 1971, pages 96-100. Such operations are performed by binary adding or subtracting groups of four binary digits each of which representing a decimal digit of the operand. Since each of these groups of four binary digits represents the decimal digits 0 . . . 9 and six invalid values A,B,C,D,E,F, correction operations are required to ensure a carry to the next higher digit position if X`9` is passed and to avoid that the result a decimal addition or subtraction includes digit positions having invalid values. In fast decimal adders such correction operations are performed in two operation cycles. In the first cycle a six correction value is added to each of the decimal digits of one of the operands in case of an addition. In the second operation cycle the raw sums generated during the first cycle are re-corrected if the result of the carry processing indicates that a correction was not necessary in a decimal digit position. For this purpose in each decimal digit position a carry-out signal of one is used to control a subtraction of six from the raw sum of the corresponding digit positions. In case of a subtraction a minus six correction is performed in the second cycle for each digit position if there is no carry-in in that position.
Thus, the known way to perform decimal additions and subtractions requires in each digit position three operations in a chain: first, a digitwise +6 operation if an addition is performed; second, a binary addition of both operands; and third, a conditional and digitwise -6 operation independent whether an addition or a subtraction is performed. This approach requires a propagation delay of 15 logical gate levels.
The time critical path of these operations resides in the highest decimal digit position for which the carry-in signal is generated at the end of the carry processing operation. Thus, the re-corrections of the sums and differences by the -6 operations require additional operation delay which limits cycle rate of the processor unit in which the decimal additions and subtraction have to be performed.